The present invention relates generally to semiconductor integrated circuit (IC) memory chips or devices, and more particularly to erasable programmable memory devices such as electrically erasable (alterable) programmable read only memories (EEPROMs).
EEPROM devices have the distinct advantage of allowing data to be written and rapidly erased electrically many times over, to permit a user to change the stored data at will while the device is in circuit. In contrast, the older PROM-type devices employ fusible links in which data is stored according to the condition of the fuses at intersections of the memory array, i.e., the condition of whether or not a fuse is blown. As such, a PROM device is, for all intents and purposes, programmable only once (that is, is non-erasable) since a blown fuse is not reparable.
Another type of erasable programmable memory, the EPROM device, requires exposure of the unhoused structure to ultraviolet (UV) light to change the electrical characteristics of a charged element in order to obtain erasure. Typically, the EPROM is housed in a windowed package (e.g., a ceramic package having a quartz window to expose the silicon), although a more recent version dubbed as "one time programmable" (OTP) is packaged in plastic without a window. As the name indicates, the windowless variety can be programmed only once. For the usual windowed EPROM that has been programmed, however, reprogramming is a major effort. If installed, the device must be removed from its in-system circuit, exposed to UV for a sufficient period of time (several hours) to assure complete erasure of the stored data, reprogrammed electrically, and then reinstalled in circuit.
The use of EEPROM devices avoids the need to subject the memory to long periods of outage for erasure. This, then, is the device of choice for applications where fast storage changes are required. In the EEPROM structure, a pair of polysilicon gates are separated by a silicon dioxide layer. The oxide also extends below the lower gate to separate it from underlying p-type silicon substrate in which a channel may be established between implanted heavily doped n-type source and drain regions. The oxide thickness between the lower gate and the silicon typically ranges up to about 100 angstroms, which is considerably less than the gate oxide thickness used for EPROM structures.
In operation of the EEPROM, a voltage of suitable magnitude applied across the very thin gate oxide layer induces tunneling of electrons from the substrate to the lower gate. A logical 1 is stored (written) when a write voltage is applied to the upper gate, thus inducing a charge on the lower gate that prevents a channel from forming during a read operation. A reversal of the write voltage causes erasure.
The endurance of an electrically erasable programmable memory refers to the number of times it may successfully be erased and rewritten (reprogrammed) during its lifetime. For all known devices, this is a finite number that depends on the processing and structural factors of the individual memory cell of the device as well as its operational environment. The typical EEPROM device marketed today "wears out", i.e., cannot be reprogrammed, after a few thousand erase/write cycles. This is a measure of its endurance.
In many current applications, it is desirable to provide greater endurance because of the number of times the memory or a particular portion or block of the memory array may be reprogrammed in normal use. Wearout of the EEPROM device used in such applications, such as for the "last number redial" feature of a standard electronic telephone set, essentially eliminates that feature from the telephone. In some instances, the eliminated feature is of such importance that the end product of which the EEPROM device is a component is rendered useless.
The use of high endurance memory to overcome this problem makes the EEPROM sufficiently more costly to be uneconomical and uncompetitive in today's global marketplace, where extremely high volume competitive applications lead to customer demands for component cost reduction.
Accordingly, it is a principal object of the present invention to provide improvements in endurance of erasable programmable memory arrays without substantially increasing the cost of such arrays.
A more specific object of the invention is to provide an erasable programmable memory array having a capability for programmable high endurance for certain applications.